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sdram_vhd_134
- Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
DDR_SDRAM_controller
- ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
DDR_SDRAM_controller
- DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides t
ref-sdr-sdram-verilog
- 标准SRD SDRAM控制器参考设计，altera提供 Verilog代码,带有使用手册，大家试试交流一下 -Standard SRD SDRAM controller reference design, altera provide Verilog code, with user manual, we try to exchange some
Sun86
- SDRAM仿真文件，主要用于测试SDRAM的控制程序是否正确。-SDRAM simulation files, mainly used for testing control procedures SDRAM is correct.
SDRAM_simulation_model
- sdram的测试程序 和读写程序 vhdl语言编写的-SDRAM testing procedures and to read and write procedures VHDL language
sdram_hr_hw
- 在FPGA硬件上实现计算机通过串口发数据给FPGA，数据保存到SDRAM中，然后又返回给计算机串口。-In FPGA hardware realize computer data through the serial port issued to FPGA, the data saved to SDRAM, and then again back to the computer serial port.
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
SDR_SDRAM_vhd
- SDR SDRAM的VHDL描述，比较详细，还有数据手册-SDR SDRAM the VHDL descr iption, more detailed, have data sheet
sdramctrl
- sdram controller vhdl
sdramctrl2
- sdram controller 2 vhdl
Micron_DDR
- DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
sdram_controller
- It s a SDRAM Controller reference design. It had been tested in many projects.
ddr2_sdram_controller
- 关于DDR2 SDRAM 控制器的相关论文资料-ddr2_sdram_controller
SDRAM_controller
- Simple SDRAM Controller.
SDRAM_design_source
- sdram的设计文档和参考源码。嵌入式开发中很难找到的源码。-sdram design documents and source code
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
c_xapp851
- 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes
Sdram_Control_4Port
- 4 multi port sdram controller